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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
Product Features
* The PI74ALVTC Family is designed for low voltage operation, VDD = 1.8V to 3.6V * Supports Live Insertion * 3.6V I/O Tolerant Inputs and Outputs * Bus Hold * High Drive, -32/64mA @ 3.3V * Uses patented Noise Reduction Circuitry * Power-Off high impedance inputs and outputs * Industrial operation at -40C to +85C * Packages available: - 48-pin 240 mil wide plastic TSSOP (A) - 48-pin 173 mil wide plastic SSOP (V) - 48-pin 300 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74ALVTC series of logic circuits are produced in the Companys advanced 0.35 micron CMOS technology, achieving industry leading speed. The PI74ALVTC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit Flip-Flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered Output Enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state in which the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to Vdd through a pullup resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver.
>C1
2
Logic Block Diagram
1OE
1
1CLK
48
1Q1
1D1
47
1D
The family offers both I/O Tolerant, which allows it to operate in mixed 1.8/3.6V systems, and Bus Hold, which retains the data inputs last state whenever the data input goes to high-impedance, preventing floating inputs and eliminating the need for pullup/down resistors.
To Seven Other Channels
24
2OE 2CLK
25
>C1
13
2Q1
2D1
36
1D
To Seven Other Channels
1
PS8356A
11/23/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Product Pin Description
Pin Name OE CLK Dx Qx GND VCC Description Output Enable Input (Active LOW) Clock Input Data Inputs 3-State Outputs Ground Power
Truth Table(1)
Inputs OE L L L H CLK H or L X D H L X X Outputs Q H L Q0 Z
Product Pin Configuration
1OE 1Q1 1Q2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
1CLK 1D1 1D2
Notes: 1. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance
GND
1Q3 1Q4
GND
1D3 1D4
VCC
1Q5 1Q6
VCC
1D5 1D6
GND
1Q7 1Q8 2Q1 2Q2
GND
1D7 1D8 2D1 2D2
GND
2Q3 2Q4
48-PIN A48 K48 V48
36 35 34 33 32 31 30 29 28 27 26 25
GND
2D3 2D4
VCC
2Q5 2Q6
VCC
2D5 2D6
GND
2Q7 2Q8 2OE
GND
2D7 2D8 2CLK
2
PS8356A
11/23/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage Range, VDD............................................ 0.5V to 4.6V Input Voltage Range, VI ................................................... -0.5V to 4.6V Output Voltage Range, VO (3-Stated) .............................. -0.5V to 4.6V Output Voltage Range, VO(1) (Active) ................... 0.5V to VDD +0.5V DC Input Diode Current (IIK) VI<0V .......................................... -50mA DC Output Diode Current (IOK) VO<0V ..................................................................................... -50mA VO>VDD .................................................................................. 50mA DC VDD or GND Current per Supply Pin (ICC or GND) ......... 100mA Storage Temperature Range, Tstg .................................... 65C to150C Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions(2)
M in. VDD VIH VIL VI VO Supply voltage High- level input voltage Low- level input voltage Input voltage Output voltage Active State Off State VDD = VDD = VDD = VDD = 3.0V to 3.6V 2.7V to 3.0V 2.3V to 2.7V 1.8V 0 -40 Operating Data Retention Only VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V - 0.3 0 0 1.8 1.2 2.0 0.8 3.6 VDD 3.6 32/64 24 18 6 10 85 mA ns/V C V M ax. 3.6 3.6 Units
Output current in IOH/IOL t/v TA
Input transistion rise or fall rate(3) Operating free- air temperature
Notes 1. Absolute maximum of IO must be observed. 2. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 As measured between 0.8V and 2.0V, VDD = 3.0V.
3
PS8356A
11/23/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted).
DC Characteristics (2.7VParame te r VIH VIL HIGH Level Input Voltage LOW Level Input Voltage IOH = -100A IOH = -12mA VOH HIGH Level Output Voltage IOH = -18mA IOH = -24mA IOH = -32mA IOL = 100A IOL = 12mA VOL LOW Level Output Voltage IOL = 18mA IOL = 24mA IOL = 32mA IOL = 64mA II IOZ IOFF IODL IODH IHOLD Input Leakage Current 3- STATE Output Leakage Power- OFF Leakage Current Output Current Low Output Current High Bus Hold Current A or B Outputs VI = VDD, or GND VO = 3.6V VI or VO 3.6V VIN = VIH or VIL, Vo = 1.5V(1) VIN = VIH or VIL, Vo = 1.5V(1) VI = 0.8V VI = 2.0V VI = 0 to 3.6V IDD IDD Quiescent Supply Current Increase in IDD per input VI = VDD or GND VDD (VI,VO) 3.6V VIH = VDD - 0.6V, Other inputs at VDD or GND 2.7 - 3.6 3.6 2.7 0 3.6 150 - 58 75 - 75 500 50 50 400 A 3.0 2.7 - 3.6 2.7 3.0 2.7 2.7 - 3.6 VDD - 0.2 2.2 2.4 2.2 2.0 0.2 0.4 0.4 0.45 0.5 0.55 5.0 10 10 334 - 114 mA A V Conditions VDD M in. 2.0 0.8 Typ. M ax. Units
3.0 3.6
Notes 1. Duration of test must not exceed 1 second with only 1 output tested at a time.
4
PS8356A
11/23/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted).
De s cription VIH VIL VOH
DC Characteristics (2.3VParame te rs HIGH Level Input Voltage LOW Level Input Voltage IOH = - 100A HIGH Level Output Voltage IOH = - 12mA IOH = - 18mA IOL = 100A VOL LOW Level Output Voltage IOL = 12mA IOL = 18mA IOL = 24mA II IOZ IOFF IODL IODH IHOLD(1) IDD DD Input Leakage Current 3- STATE Output Leakage Power- OFF Leakage Current Output Current Low Output Current High Bus Hold Current A or B Outputs Quiescent Supply Current Increase in IDD per input VI = VDD or GND VO = 3.6V VI or VO 3.6V VIN = VIH or VIL, VO = 1.5V(2) VIN = VIH or VIL, VO = 1.5V(2) VI = 0.7V VI = 1.7V VI = VDD or GND VDD (VI,VO) 3.6V VIH = VDD - 0.6V, Inputs at VDD or GND 2.3 - 2.7 2.7 2.3 0 2.7 110 - 30 90 - 90 40 40 400 A 2.3 2.3 - 2.7 Conditions VDD M in. 1.6 0.7 VDD - 0.2 1.8 1.7 0.2 0.4 0.5 0.55 5.0 10 10 264 - 60 mA A V Typ. M ax. Units
2.3 2.3 - 2.7
2.5
Notes: 1. Not Guaranteed 2. Duration of test must not exceed 1 second with only 1 output tested at a time.
5
PS8356A
11/23/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted).
De s cription VIH VIL VOH
DC Characteristics (1.8VParame te rs HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = - 100A IOH = - 6mA IOL = 100 A IOL = 6 mA VI = VDD or GND VO = 3.6V VI = VO 3.6V VIN = VIH or VIL, VO = VI = 0.4 VI = 1.3 VI = VDD or GND VDD (VI,VO) 3.6V VI = VDD - 06V, Other inputs at VDD or GND 1.8 0.9V(2) VIN = VIH or VIL, VO = 0.9V(2) 2.3 1.8 0 1.8 50 - 14 50 - 50 20 20 400 A 1.8 Conditions VDD 1.8 - 2.3 M in. 0.7 x VDD 0.2 x VDD VDD - 0.2 1.4 0.2 0.3 5.0 10 10 137 - 34 mA A V Typ. M ax. Units
VOL II IOZ IOFF IODL IODH IHOLD(1) IDD DD
LOW Level Output Voltage Input Leakage Current 3- State Output Leakage Power- OFF Leakage Current Output Current Low Output Current High Bus Hold Current A or B Outputs Quiescent Supply Current Increase in IDD per input
Notes: 1. Not Guaranteed 2. Duration of test must not exceed 1 second with only 1 output tested at a time.
6
PS8356A
11/23/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
AC Electrical Characteristics
TA = -40C to +85C, CL = 50pF, RL = 500 VDD = 3.3V 0.3V Symbol fMAX tPLH, tPHL tPZH, tPZL tPHZ, tPLZ tOSHL, tOSLH Parame te r Maximum Clock Frequency Prop Delay, CLK to Q Output Enable Time Output Disable Time Output to Output Skew(1) M in. 250 1.0 1.0 1.0 3.2 3.2 3.4 0.5 M ax. VDD = 2.5V 0.2V M in. 250 1.5 1.0 1.0 4.2 4.7 3.8 0.5 M ax. VDD = 1.8V M in. 250 1.5 1.5 1.5 4.8 5.0 4.0 0.5 ns M ax. Units MHz
Notes: 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH or LOW (tOSHL) or LOW to HIGH (tOSLH).
AC Setup Requirements
TA = -40C to +85C, CL = 50pF, RL = 500W VDD =3.3V 0.3V Symbol tSU tH tW Parame te r Setup Time Hold Time Pulse Width M in. 1.0 0.5 1.5 Typ. VDD =2.5V 0.2V M in. 1.0 0.5 1.5 Typ. VDD =1.8V M in. 1.0 1.0 1.5 ns Typ. Units
Capacitance
Symbol CIN COUT CPD Parame te r Input Capacitance Conditions VDD = 1.8, 2.5V or 3.3V, VI = 0V or VDD VI = 0V or VDD, F = 10 MHz VDD = 1.8V, 2.5V or 3.3V TA = +25C Typical 6 7 20 pF Units
Output Capacitance VI = 0V or VDD, VDD = 1.8V, 2.5V or 3.3V Power Dissipation Capacitance
7
PS8356A
11/23/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Test Circuits and Switching Waveforms
Parameter Measurement Information (VDD = 1.8V - 3.6V)
Switch Position
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1
Open 2 x VDD GND
Pulse Width
VDD Low-High-Low Pulse tW VDD VDD/2 0V
Setup, Hold, and Release Timing
Data Input tSU Timing Input tH VDD VDD/2 0V VDD VDD/2 0V
High-Low-High Pulse
VDD/2 0V
Propagation Delay
VDD VDD/2 Input tPLH Output tPHL tPLH VDD Opposite Phase Input Transition VDD/2 0V tPHL 0V VDD VDD/2 VOL
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tr 2ns, tf 2ns, measured from 10% to 90%, unless otherwise specified. D. The outputs are measured one at a time with one transition per measurement.
Enable Disable Timing
VDD Output Control
(Active LOW)
VDD/2 tPZL VDD VDD/2 +0.15V tPZH VDD/2 0V tPHZ -0.15V VOH VOL tPLZ 0V VDD
Output Waveform 1 S1 at 2xVDD
(see Note B)
Output Waveform 2 S1 at GND
(see Note B)
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
8
PS8356A 11/23/98

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